1. Field of the Invention
The present invention relates to a thin-film device comprising a lower conductor layer, a dielectric film and an upper conductor layer that are stacked, and to a method of manufacturing such a thin-film device.
2. Description of the Related Art
With increasing demands for reductions in dimensions and thickness of high frequency electronic apparatuses such as cellular phones, reductions in dimensions and profile of electronic components mounted on the high frequency electronic apparatuses have been sought. Some of the electronic components comprise capacitors. Each capacitor typically incorporates a dielectric layer and a pair of conductor layers disposed to sandwich the dielectric layer.
To achieve reductions in dimensions and profile of an electronic component comprising a capacitor, important factors are a reduction in area of a region in which the pair of conductor layers are opposed to each other with the dielectric layer disposed in between and a reduction in the number of layers making up the capacitor. Basically, in prior art, a material having a high permittivity is used as a dielectric material forming the dielectric layer and the thickness of the dielectric layer is reduced to achieve a reduction in area of the above-mentioned region and a reduction in the number of the layers making up the capacitor.
As conventional electronic components comprising capacitors, a thin-film capacitor disclosed in Japanese Published Patent Application (hereinafter referred to as JP-A) 2003-347155 and a thin-film capacitor element disclosed in JP-A 2003-17366 are known. The thin-film capacitor disclosed in JP-A 2003-347155 incorporates a lower electrode layer, a dielectric layer and an upper electrode layer formed one by one on a substrate through the use of thin-film forming techniques. The thin-film capacitor element disclosed in JP-A 2003-17366 incorporates a lower electrode, a dielectric layer and an upper electrode formed one by one on a substrate through the use of thin-film forming techniques. JP-A 2003-17366 discloses a technique in which the top surface of the lower electrode and that of an insulator layer disposed around the lower electrode are flattened to form the dielectric layer on the flattened top surfaces. An electronic component formed through thin-film forming techniques such as the above-mentioned thin-film capacitor and thin-film capacitor element is called a thin-film device in the present patent application.
JP-A 11-168306 discloses an element comprising: a dielectric substrate; a multilayer thin-film electrode made up of thin-film conductor layers and thin-film dielectric layers alternately stacked on the dielectric substrate with a bonding layer disposed between every adjacent thin-film conductor layer and thin-film dielectric layer; and a flattening film disposed between the dielectric substrate and the multilayer thin-film electrode. This publication discloses a technique in which polishing processing is performed on the top surface of the flattening film so that the surface roughness Ra of the top surface of the flattening film is 0.05 μm or smaller.
Since the dielectric layer of the thin-film device comprising a capacitor is formed through thin-film forming techniques, it is possible to reduce the thickness of the dielectric layer and to thereby reduce the profile of the thin-film device. However, if the thickness of the dielectric layer is reduced in the thin-film device comprising a capacitor, there arise problems that the withstand voltage of the capacitor is reduced and that variations in withstand voltage of the capacitor among products are increased. These problems will now be described in detail with reference to FIG. 14.
FIG. 14 is a cross-sectional view illustrating an example of configuration of a thin-film device comprising a capacitor. The thin-film device of FIG. 14 comprises: a lower conductor layer 102 disposed on a substrate 101; a dielectric layer 103 disposed on the substrate 101 and the lower conductor layer 102; and an upper conductor layer 104 disposed in a region sandwiching the dielectric layer 103 with the lower conductor layer 102. The thin-film device is fabricated by forming the lower conductor layer 102, the dielectric layer 103 and the upper conductor layer 104 in this order on the substrate 101 through the use of thin-film forming techniques.
In the thin-film device of FIG. 14, a ceramic substrate is used as the substrate 101, for example. In this case, even if the top surface of the substrate 101 is polished, there exist a number of minute holes in the top surface of the substrate 101. Accordingly, the surface roughness of the top surface of the substrate 101 is great. If the lower conductor layer 102 is formed on such a substrate 101, the surface roughness of the top surface of the lower conductor layer 102 becomes great, too, like the top surface of the substrate 101. If the surface roughness of the top surface of the lower conductor layer 102 is great, the thickness of the dielectric layer 103 is made nonuniform. Consequently, a portion that is extremely small in thickness develops in the dielectric layer 103, and insulation in the portion is degraded, which may result in an extreme reduction in withstand voltage of the capacitor. In such a case, a short-circuit failure of the capacitor resulting from a puncture of the dielectric layer 103, for example, is likely to occur. Furthermore, if the thickness of the dielectric layer 103 is nonuniform, variations in withstand voltage of the capacitor among products are increased.
In a case in which the thin-film device is designed for high frequency applications, if the surface roughness of the top surface of the lower conductor layer 102 is great, the skin resistance of the lower conductor layer 102 increases, and the signal transmission characteristic of the lower conductor layer 102 may be thereby degraded.
As described above, JP-A 2003-17366 teaches flattening the top surfaces of the lower electrode and the insulator layer disposed around the lower electrode and forming the dielectric layer on the flattened top surfaces. However, this publication does not teach the allowable degree of surface roughness of the top surface of the lower electrode in relation to the thickness of the dielectric layer.
As described above, JP-A 11-168306 discloses the technique in which the flattening film is provided between the dielectric substrate and the multilayer thin-film electrode, and polishing processing is performed on the top surface of the flattening film so that the surface roughness Ra of the top surface of the flattening film is 0.05 μm or smaller. However, this publication does not teach the allowable degree of surface roughness of the top surface of the flattening film in relation to the thickness of the thin-film dielectric layer.
The foregoing problems apply not only to thin-film devices comprising capacitors but also to thin-film devices in general each comprising a substrate and a lower conductor layer, a dielectric film and an upper conductor layer that are stacked on the substrate.